1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor memory device having bit lines for inputting/outputting data of memory cells.
2. Description of the Background Art
Recently, in equipments for office automation, equipments for engineering work stations and the like, an SRAM (Static Random Access Memory) having large capacity and operating at high speed has come to be used as a cache memory. Accordingly, higher speed of operation and larger capacity of the SRAM has been desired. In order to meet such a demand, a semiconductor memory device having a T-shaped bit line configuration is proposed in Japanese Patent Laying-Open No. 4-228188 and in "Bit Line Configuration Suitable for Very High Speed SRAM--T-Shaped Bit Line Configuration and Application to BiCMOS 256K TTL SRAM", Tsushingakkai Kenkyukai (Society of Communication Engineers Workshop) (CAS91-58, SDM91-63, ICD91-67). In the T-shaped bit line configuration, the bit line includes a first metal layer and a second metal layer connected to each other, and word lines and bit lines of the second metal layer are arranged parallel to each other. As a result, by virtue of the T-shaped bit line configuration, the column pitch is released in the ratio of the number of columns with respect to the number of rows in one block, whereby the column pitch can be widened, which contributes to higher degree of integration.
The aforementioned conventionally proposed semiconductor memory device will be described with reference to the figures. FIG. 13 is a block diagram showing the structure of a memory cell array and peripheral portion of a conventional semiconductor memory device.
Referring to FIG. 13, the convention semiconductor memory device includes bit line peripheral circuits 101 to 103, a row decoder 104, a memory cell MC, bit lines BL1 to BLn and /BL1 to /BLn, word lines WL1 to WLm, and bit line signal input/output lines L1 to Ln and /L1 to /Ln.
Word lines WL1 to WLm are provided crossing a plurality of bit lines BL.sub.1 to BLn and /BL1 to /BLn. Adjacent bit lines constitute a bit line pair ("/" represents a complementary signal line). For example, bit lines BL1 and /BL1 form one bit line pair, and bit lines BL2 and /BL2 form a bit line pair. At each cross point of the bit line pair and the word line, a memory cell MC which is a static memory cell, is arranged, thus providing a memory cell array.
Each of the word lines WL1 to WLm receive an output signal from row decoder 104. Row decoder 104 decodes a row address signal applied through an address buffer (not shown) and selects one of the word lines WL1 to WLm. At one end of each of the bit line pairs BL1, /BL1, . . . , BLn, /BLn, a bit line peripheral circuit 101 is provided. At the other end of each of the bit line pairs BL1, /BL1, . . . , BLn, /BLn, a bit line peripheral circuit 102 is provided.
Further, bit line signal input/output lines L1, /L1, . . . , Ln, /Ln are provided crossing bit lines BL1, /BL1, . . . , BLn, /BLn. Bit line signal input/output lines L1, /L1, . . . , Ln, /Ln are connected to the corresponding bit lines BL1, /BL1, . . . , BLn, /BLn, and inputs a prescribed signal to the corresponding bit line, or outputs a signal obtained from the corresponding bit line to the outside of the memory cell array. At right end of each of the bit line signal input/output lines L1, /L1, . . . , Ln, /Ln drawn out of the memory cell array, a bit line peripheral circuit 103 is connected.
In the conventional semiconductor memory device having the T-shaped bit line configuration, the bit line peripheral circuit 103 can be arranged because the bit line signal input/output lines L1, /L1, . . . , Ln, /Ln are provided, and therefore the bit line peripheral circuits can be arranged dispersed in wider area. As a result, a large scale bit line peripheral circuit can be laid out without widening the bit line pitch. Further, when a bit line peripheral circuit of a fixed area is to be provided, the density of the memory cell array can be increased, realizing highly integrated semiconductor memory device.
The bit lines and the bit line signal input/output lines mentioned above will be discussed in greater detail. FIG. 14 shows line arrangement on a memory cell array of 4 rows.times.4 columns of the semiconductor memory device shown in FIG. 13.
Referring to FIG. 14, 16 memory cells MC each corresponding to 1 bit are arranged in 4 rows.times.4 columns. Bit lines BL0, /BL0, . . . , /BL3 and /BL3 are formed by a first metal layer, on the memory cell array. Bit line signal input/output lines L, /L are formed by the second metal layer, orthogonally crossing bit lines BL0, /BL0, . . . BL3 and /BL3. In the second metal layer, shield lines GND0 to GND3, input/output data lines IO and /IO, and a global word line GWL are arranged parallel to the bit line signal input/output lines L and /L. Bit lines BL0, /BL0, . . . , BL3 and /BL3 and corresponding bit line signal input/output lines L and /L are connected through through holes TH1 and TH2. In FIG. 14, for example, bit line BL1 is connected to bit line signal input/output line L via thorough hole TH1, while bit line /BL1 is connected to bit line signal input/output line /L via through hole TH2.
A signal of a large amplitude flows through global word line GWL, while a signal of a small amplitude flows through bit line signal input/output lines L and /L and input/output data lines IO and /IO. Therefore, in order to prevent malfunction caused by the signal of the small amplitude receiving coupling noise from the signal of large amplitude, shield lines GND0 to GND3 which are low impedance shield lines at the shield potential are interposed.
Line pattern on the memory cell array when the above described semiconductor memory device is integrated to a higher degree will be described. FIG. 15 is a second diagram showing lines on the memory cell array of 4 rows.times.4 columns of the semiconductor memory device shown in FIG. 13. When the degree of integration of the memory cell array is increased, it becomes necessary to widen the width of bit lines BL1 and /BL1 around the through holes TH1 and TH2 so as to provide overlapping margin of through holes TH1 and TH2 and bit lines BL1 and /BL1, as shown in FIG. 15. In other words, higher degree of integration of the memory cell array can be implemented by making wider the bit lines BL1 and /BL1 around the through holes as shown in FIG. 15.
However, if the memory cell array of the conventional semiconductor memory device described above is to be integrated to a still higher degree, the space between bit lines around the through hole becomes too narrow, and hence there is a limit in increasing the degree of integration. FIG. 16 shows a specific layout pattern of the memory cell array of the semiconductor memory device shown in FIG. 13. When the width of bit line signal input/output lines L and /L is made 1.0 .mu.m and space therebetween is set to 0.6 .mu.m, the width of bit lines BL and /BL are made 0.6 .mu.m and the space therebetween is set to 0.9 .mu.m, one side of the through holes TH1 and TH2 is made 0.6 .mu.m and the margin of bit lines BL and /BL for the through holes TH1 and TH2 are made 0.3 .mu.m in order to further increase the degree of integration of the memory cell array of the semiconductor memory device, then the minimum space between the bit lines BL and /BL defined by the portion A would be 0.5 .mu.m. If the minimum space between the lines is set to 0.6 .mu.m, the portion A, which is 0.5 .mu.m, does not satisfy this condition, and hence higher degree of integration is impossible.